Cleveland, OH - February 1, 2000 - Efficient Channel Coding announced today that it has developed a Turbo Code Library that allows users to easily integrate and test various Turbo Product Codes (TPCs) into their Elanix (www.elanix.com) SystemView designs.

Turbo codes are an exciting new class of methods describing the iterative decoding of Forward Error Correction (FEC) codes. Their performance can take error correction within a dB of the Shannon limit for many combinations of code rate and block size. This capability allows turbo codes to replace many Viterbi and Reed-Solomon codes in existing and emerging applications. A number of companies and universities have experimented with turbo codes over the past five years with promising results, but little practical hardware. This changed in late 1998, as Advanced Hardware Architectures Inc. announced Turbo Product Code (TPC) chips developed in conjunction with Efficient Channel Coding, Inc. Efficient Channel Coding has pioneered the development of low complexity, high performance decoding algorithms that Advanced Hardware Architectures has translated to silicon.

The Turbo Code Library V1.0 allows users to easily integrate and test various Turbo Product Codes (TPCs) into their simulations under SystemView. The tokens feature a rich set of parameters to enable a wide range of code rates, coding gains, block sizes, and latency. Moreover, metric computer tokens are provided to allow interfacing with higher order modulation.

Near term future versions of the Turbo Code Library will support other classes of iterative decoders including Turbo Convolutional Codes (TCCs) for 3G communications systems. A functional simulation of the only commercially available TPC ASIC, the Advanced Hardware Architectures AHA4501 Astro Turbo Product Code Encoder / Decoder, will be available soon as well.

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