Combining telecommunication standards and advanced FEC technologies to meet customer requirements.

This project demonstrates our ability to combine telecommunication standards and apply advanced FEC technologies to meet customer requirements. Based on our analysis, we selected optimum code which provided the best coding gain at the lowest power consumption at both the transmitter and receiver.

The system was designed to transmit and receive a pair of STM-4 level signals (622 Mbps) and a pair of E1 signals (2.048 Mbps) that were multiplexed together and protected with a 7/8 rate Low Density Parity Check (LDPC). The inclusion of the advanced LDPC error correction code met the power specifications by reducing the transmitter power while still maintaining the link at the lower signal to noise ratios.

The encoder card accepted a pair of STM-4 signals and a pair of E1 signals. The data was multiplexed, formed into LDPC blocks, encoded and scrambled. A unique header was added to allow the receiver to align to the LDPC blocks and differentiate between the I & Q modulated data. The output was a non-standard optical bit stream at 1.452 Gbps.

The decoder board receives I & Q data from the demodulator, resolves phase rotation, and aligns and decodes the data. The resulting data is demultiplexed into the original STM-4 pair and E1 pair.

The project presented other unique challenges due to the size and power constraints. Both the encoder and decoder were required to operate in a sealed box with no forced error cooling. Careful thermal management and board design allowed heat to dissipate through the printed circuit board and directly couple to the chassis.