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9610A DVB-S2 Modulator IP core

9610A DVB-S2 Modulator IP core

The 9610A DVB-S2 modulator core is designed for unprecedented bandwidth and power efficiency for direct broadcast satellite (DBS), digital satellite news gathering (DSNG), broadband VSAT networks, and enhanced mobile communication networks. It is a completely customizable forward link modulator core with integrated LDPC + BCH encoder.

 This modulator is already designed into transmitters and transceivers and will continue to be employed in future variants of DVB-S2 products.
 
  • Designed in Verilog RTL
  • Uses simple, readily-available building blocks
  • No-cost in all families of both Altera and Xilinx FPGAs and in ASIC libraries
  • No 3rd party IP cores
 The blocks of the ECC 9610A DVB-S2 modulator core include these design elements:
  • Easily reconfigure for specific application requirements
  • Low-complexity, streamlined mostly-serial architecture
  • Higher-complexity, highly-parallel architecture
  • Logic and memory use information for a target application
  • Features can be turned on/off or modified for specific applications
 
 

Standards Compliance
DVB-S2
Fully compliant
DVB-S
Fully compliant (optional)

Waveform Characteristics
Modulations

QPSK, 8-PSK, 16-APSK and 32-APSK (optional). Supports pre-distortion to combat link impairments (optional).
Code rates

¼, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10. Follows DVB-S2 modulation and block-size restrictions.
Block-sizes
16200 bits (Short) and 64800 bits (Normal)
Symbol rates

0.1 – 62.49 Msym/s (for nominal 125 MHz core clock)
Pilots
On / Off on a frame-by-frame basis
Dummy frames
Inserted automatically as needed
Baseband padding / null frames

Inserted automatically as needed (optional)
Adaptive symbol rate
(optional)
RRC filter roll-offs
0.35, 0.25 and 0.2
Modes
Constant Coding and Modulation (CCM)

Adaptive Coding and Modulation (ACM) within a block-size

Variable Coding and Modulation (VCM) within a block-size

Spectral Characteristics
Output frequency
Baseband or Low-IF (optional)
Low-IF frequency specifications
50 MHz to 180 MHz in steps of 1 Hz.
Implementation Options
Altera FPGAs
Stratix, Stratix-II, Cyclone III family
Xilinx FPGAs

Virtex-II, Virtex-II pro, Virtex-4, Virtex- 5 and Spartan-3 families
ASICs
Any technology
 

 


©2009 ECC, Inc.